1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to a semiconductor memory apparatus which adopts data bus inversion.
2. Related Art
As the data processing speeds of a central processing unit (CPU) and a graphic processing unit (GPU) are gradually increased, semiconductor memory apparatuses capable of operating at a high frequency are needed inevitably. However, in the semiconductor memory apparatuses operating at a high frequency band, the performances of the semiconductor memory apparatuses are likely to deteriorate due to noise of data. In order to solve this problem, the strength of a data driver has been increased or design has been conducted in consideration of a clock margin. Nevertheless, problems are still caused in that noise is generated and misoperation occurs due to an increase in the number of data switching times in the high frequency band.
Accordingly, a data bus inversion (hereinafter, referred to as “DBI”) scheme capable of minimizing the number of data switching times has been proposed in the art. In the DBI scheme, what number of data bits among a predetermined number of data bits, for example, 8 data bits induce current flow in transistors of a data output buffer is determined, and if the number of data bits having a logic value which can induce the current flow is large, the number of data bits are inverted so that current consumption can be reduced.
FIG. 1 is a block diagram schematically illustrating the configuration of a conventional semiconductor memory apparatus. A conventional semiconductor memory apparatus 10 includes a data bus inversion determination unit (hereinafter, referred to as a “DBI determination unit”) 11 and a data output unit 12. The DBI determination unit 11 is enabled by receiving a mode signal ‘mode’ which is enabled from a mode register set. The DBI determination unit 11 receives data GIO<0:7> which are transmitted from data input/output lines, and generates a determination signal ‘flag’ for determining whether to invert data, depending upon the logic levels of the data GIO<0:7>. The data output unit 12 has a plurality of data output drivers DQ1 through DQ8. The data output unit 12 receives the data GIO<0:7> transmitted from the data input/output lines and the determination signal ‘flag’, and determines whether to output the data by inverting it or passing the data through as is, that is, simply transmitting the data. If the mode signal ‘mode’ is enabled, the determination signal ‘flag’ is transferred to a chipset which is connected with the semiconductor memory apparatus 10. Therefore, even though inverted output data are outputted, the chipset can recognize that the data having levels opposite to those of the inverted output data are precise data.
Nonetheless, in the conventional semiconductor memory apparatus, since whether to output the data by inverting or non-inverting (i.e. transmitting) them is determined and data can be inverted only in the data output unit 12, a problem is caused in that current consumption is substantial due to toggling of the data input/output lines for transmitting data. Also, in the conventional art, due to an interfacing problem which is likely to occur between the semiconductor memory apparatus and the chipset, the inversion operation can be performed only in a DBI mode by receiving the mode signal ‘mode’ which is generated from the mode register set, and cannot be performed in a normal mode.